Design styles based on multiplexors have become very popular due to their good testability. Starting from a function description as a Binary Decision Diagram (BDD) the circuit is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under the Stuck-At Fault Model (SAFM). Even though free of redundancies, the resulting circuits may contain hard to test faults, since the fault detection probability is very low. In this paper we present optimization techniques for circuits derived from BDDs such that the final circuit has good random pattern testability. The BDD ordering is optimized and the input probabilities are varied. The algorithms operate at a high level of abstraction and make use of the compact function representation as BDDs. Experiments are given to demonstrate the efficiency of the approach.
展开▼
