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Optical Characterization and Defect inspection for 3D stacked IC technology

机译:3D堆叠IC技术的光学表征及缺陷检测

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Advanced packaging technologies are rapidly evolving and 3D architectures requires new inspection and metrology techniques. Existing techniques need to be improved but new techniques must be developed to address new challenges induced by the last fabrication processes. To increase the development speed, it is a big advantage that metrology and defect inspection need to be present on the same platform and a flexible tool, with multi sensors, to be more versatile facing the different step of the process will be presented in this paper As 3D IC devices utilize TSVs for direct interconnect, the depth, top and bottom CD (critical diameter) of such TSVs with a diameter as small as 5 μm with a high aspect ratio is characterized. During wafer temporary bounding, which is an handling technique that allows wafer thinning with a thickness of less than 100 μm, by selecting the most sensitive sensor, determination of the thickness of each layer of the stack could be determined at the same time: silicon substrate, thin glue layer of few microns only and carrier which could be silicon or glass. After back-side processing and wafer thinning, the determination of the remaining silicon thickness (RST) below the TSV could be determined. Moreover back side roughness after grinding is also determined. After wafer thinning process, the TSVs are revealed at the back side of the wafer, leaving to appear copper pillars. The pillars height and co-planarity measurements are then addressed. Post CMP process control will be addressed by full field interferometry especially prior Copper to Copper direct bonding. Concerning the defect inspection, the NIR microscopy is used to control die to wafer stacking process, to reveal voids in the glue and cracks on the grinded silicon substrate. In this paper, we will present fast and nondestructive optical sensors based on low coherence infrared and white light interferometry and spectrometry techniques. These different sensors mounted on the same tool allow characterizing specifically and with an excellent sensitivity the different process steps described above. Concerning the defect inspections, techniques based on infrared microscopy and images techniques processing will be detailed and results will be presented to illustrate the possibilities of this inspection by microscopy.
机译:先进封装技术正在迅速发展和3D架构需要新的检测和计量技术。现有技术需要改进,但新的技术必须发展以解决最后的制造工艺引起的新的挑战。为了提高开发速度,这是一个很大的优点是,计量和缺陷检验需要存在相同的平台和灵活的工具上,多传感器,更通用的面向过程的不同步骤将在本文呈现作为3D IC器件利用用于直接互连,深度,顶部和此类TSV的底部CD(临界直径)的TSV的直径小至5微米的高纵横比的特征。在晶片临时边界,这是一个处理技术,其允许晶片减薄的厚度为小于100μm,通过选择最敏感的传感器,叠层的每一层的厚度的确定可以在同一时间被确定:硅衬底,几微米的薄胶层仅和载体,其可以是硅或玻璃。背面侧处理和晶圆减薄之后,TSV下面剩余的硅厚度(RST)的确定可以被确定。此外背面粗糙度研磨后也被确定。晶片薄型加工后,将硅通孔显露在晶片的背面侧,使出现铜柱。然后,将柱子高度和共面性的测量解决。 CMP后过程控制将被满场干涉尤其现有铜被寻址到铜直接接合。有关的缺陷检查中,NIR显微镜被用来控制管芯到晶片堆叠工艺,以显示经研磨硅衬底上在胶空隙和裂缝。在本文中,我们将提出快速和基于低相干无损光学传感器红外和白光干涉和分析技术。这些不同的传感器安装在相同的工具允许特异性和与上述不同的工艺步骤的优异的灵敏度特性。关于缺陷的检查,基于红外显微镜和图像的技术的处理技术进行详细说明和结果将提交通过显微镜来说明这个检验的可能性。

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