Methodology to Correlate Defect Reduction Systems to Electrical Test Data via Artificially Manufactured Defects

摘要

This paper describes a methodology for correlating physical defect inspection/navigation systems with electrical bitmap data through the fabrication of artificial defects via reticle alterations or circuit modifications using an inline FIB. The methodology chosen consisted of altering decommissioned reticles to create defects resulting in both open and shorted circuits within areas of an AMD microprocessor cache. The reticles were subsequently scanned using a KLA SL300HR StarLight inspection system to confirm their location, while wafers processed on these reticles were scanned at several layers using standard inline metrology. Finally, the wafers were electrically tested, bitmapped, and physically deprocessed. All defect data was then analyzed and cross-correlated between each system, uncovering some important system deficiencies and learning opportunities. Data and images are included to support the significance and effectiveness of such a methodology.