We introduce a novel Quadrature Direct Digital Frequency Synthesizer (QDDFS) architecture optimized for hardware implementation. It is based on a hardware efficient phase-to-sinusoid amplitude converter split into two parts: sine and cosine generators, each covering angles in the first octant. Quadrature sinusoids are reconstructed by mapping any angle to the first octant and selecting the appropriate generator. The converter's complexity is kept low by approximating each function with equal-length piecewise-continuous linear segments, Segment slopes and initial amplitudes are carefully selected to maximize the synthesizer's Spurious Free Dynamic Range (SFDR). The architecture is particularly well suited for low power wireless frequency-hopping communication systems. Examples for synthesizers achieving 60 and 72 dBc of SFDR are given, and it is shown mat system complexity compares favorably with previous approaches.
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