The maximum current slew rate of Pentium 4 microprocessor is 510A/μs and it will reach more than IA/ns for future generations. However, voltage regulator module (VRM) is always too slow (50A/μs) to react and results in output voltage spikes. The existing of large socket inductance between motherboard and microprocessor package generates large voltage spike under load-change transient due to its current response delay. A new active transient current compensation is presented to limit voltage spike within 1.5% variation in load-change transient when microprocessor operates at 1V, 100A and 2A/ns of current slew rate with the package capacitance decreasing to less than one-half of Pentium 4 level. Therefore, the total voltage variation is limited within 3%.
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