The beeping channel model is a multiple access channel (MAC) model where active nodes can only send/hear a "jamming" signal (i.e. a beep) through the communication channel in each time slot [2]. A listening node hears a beep signal if at least one node is beeping; otherwise it hears nothing. The beeping model was recently proposed to model carrier-sensing-based wireless communication [2], and the Delta-Notch signalling mechanism between biological cells [1]. The motivation of our work, however, is to design efficient digital circuits. It turns out that the beeping channel model well characterizes the behaviors of a group of sequential logic modules connected by a logical-OR gate. A strictly synchronized global clock is available in such a circuit. In a clock cycle, a high electrical level in each input wire of the OR gate corresponds to the choice to beep made by the module connecting to this input wire while a low level corresponds to the choice not to beep. The output of the OR gate is wired back to each module as the source signal in the next cycle. We focus on deterministic protocols, which is preferred in hardware design and other applications requiring safety guarantee.
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