New ATPG algorithm for i{sub}(DDT)-based testing

摘要

In this paper we present a new ATPG algorithm and its software implementation for the automatic generation of input vector pairs specific for I{sub}(DDT)-based test methods. The algorithm attempts to switch every net in the circuit, to minimize the total number of required test vectors and to minimize the switching activity in the circuit. We present the results of the application of the ATPG to the ISCAS'85 benchmark circuits and show the switching profiles of the benchmark circuits.