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Residue signed-digit arithmetic circuit with a complement of modulus and the application to RSA encryption processor

机译:RSA加密处理器的补体和应用程序的残留符号数字算术电路

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A fast residue arithmetic circuit using a complement of modulus in a signed-digit (SD) number representation is proposed. For a large modulus M with a length of (p+1)-bit used as a keg in RSA public-keg crypto-system, a complement of M, M=2{sup}p-M, with the p-digit SD number representation is used to calculate the modular operations. Thus, a modular addition can be implemented by using two SD adders, one for SD addition and another for the modular operation with the complement M. A modular multiplication is performed by repeating the modular shift and the modular addition operations in a radix-two SD number representation. By using a booth recording method, the speed of a modular multiplication becomes twice as fast as. The circuit design and simulation results by VHDL show that high speed RSA public-keg encryption processor can be implemented by applying the presented residue arithmetic circuit.
机译:提出了一种快速残留的算术电路,使用符号位数(SD)数表示中的模数互补。对于长度(p + 1)贝格的大型模数m,用作RSA公钥加密系统中的柯格,CM,M = 2 {SUP} PM的补码,具有p型SD号表示用于计算模块化操作。因此,可以通过使用两个SD加法器来实现模块化加法,一个用于SD加法,另一个用于使用补码M的模块化操作。通过重复模块化移位和基数-2 SD中的模块化加法操作来执行模块化乘法数字表示。通过使用展位记录方法,模块化乘法的速度变得两倍。 VHDL的电路设计和仿真结果表明,通过应用所呈现的残留算术电路,可以实现高速RSA公钥加密处理器。

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