We have presented a new methodology for SoC toplevel validation, aiming at verifying correct IP interoperability. The basic idea is to build a nondeterministic machine generating all the tests in a test plan in a formal and systematic way. The machine is built using all the features of Esterel Studio, a system used in many other fields to build large hierarchical FSMs. The system is modeled at a very high transactional level, ignoring details about what the IPs really compute. Cycle-accurate or bus-cycle accurate models would be intractable and inappropriate for the sole purpose of interoperability verification. Symbolic tests are generated using state-of the-art BDD-based sequential exploration algorithms. They are translated into actual executable tests by application specific scripts before being run on the SoC validation platform. The main advantage of our method compared to manual or random ones is that we know exactly what we test. First, we have a precise model of the test plan, second, we guarantee to cover 100% of it. Manual techniques cannot offer such a result, since analyzing the potential interactions between IPs is not a human-feasible tasks. Random techniques can be used to explore the design more heavily than manual techniques, but they are also limited by the fact that their actual IP interaction coverage cannot be measured. As a byproduct, the models also provide good graphical documentation of how the IPs are configured and of how they interact. Since the model is built in a completely modular way, the IP models can be reused together with the IPs.
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