High Clock Rate CMOS Digital Pipeline Multiplier/Accumulator for Serial Correlator

摘要

With SDL circuits it is possible to achieve simply high clock rate latches and logic gates. By these one may conceive pipeline half- and full-adders or accumulators. The multiplier/accumulator part of a correlator channel ("lag"), which processes successive time-moment samples, matches very well with a pipeline technique. For digital correlators, used with periodical signal extraction from noise, a two-bit digitizing proved as satisfactory. In this case, the multiplication of two-bit sign-magnitude numbers may be achieved simply by logic gates. The work analyses the pipeline half- and full-adder, half-and full-accumulator, two pipeline multiplier variants and then, an accumulator, only realised with original SDL circuits. Timing requirements for all these schemes are established. The correlator has been implemented within 0.18μm CMOS process; the chip includes 128 lags and work with up to 1GHz clock rate.