A methodology for testing high-performance circuits at arbitrarily low test frequency

摘要

This paper presents a methodology for testing high-performance circuits with a low-speed clock in test mode. Using this technique, the frequency of the 50% duty cycle test mode clock can be reduced with virtually no lower limit. This poses very little requirements on automatic test equipment (ATE) and facilitates the testing process. A CMOS implementation that achieves 50ps accuracy is also presented. This technique targets designs using design for testability (DFT) and/or built-in self test (BIST) techniques.