High bandwidth low latency chip to chip interconnects using high performance MLC glass ceramic POWER4 MCM

摘要

This paper describes a high performance multi-layer ceramic (MLC) Four Chip Glass-Ceramic Multi-Chip Module (MCM) that achieves very high bandwidth and low latency performance by incorporating unique design approaches and features. These include leveraging an I/O ring pattern arrangement using the fine line capability of IBM's High Performance Glass Ceramic (HPGC) and the capability to use 30+ wiring layers with isolating reference planes. The attendant signal integrity is assured by providing a tailored reference structure to control impedance and cross-talk coupling while maintaining the chip C4 I/O area density without requiring thin-films or degrading the power integrity.