Low Power Viterbi Decoder Implementation for CDMA Applications

摘要

This paper presents a low-power FPGA design of a Viterbi decoder for wireless communications applications. In CMOS technology the major contribution to power dissipation is attributed to the switching of signal values. To address the reduction of dynamic power dissipation at the logic level two methods are considered namely, toggle filtering and clock-gating. Toggle filtering prevents unnecessary switching by making the input available to a module when required. In a clock-gating scheme only a register whose value needs to be updated is enabled and allowed to change contents at the cost of an extra logic gate resulting in power saving. At the architectural level the approach adopted aims at minimizing the area and power by matching the computational resources with the data throughput requirements. The power calculation results show that the proposed design methodology reduces the power dissipation of a Viterbi decoder by about 25 percent as compared with one without the low-power design provisions.