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Optical Multi-Token-Ring Networking Using Smart Pixels With Field Programmable Gate Arrays (EPGAs)

机译:使用具有现场可编程门阵列(EPGA)的智能像素的光多象环网络

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This research explores architectures and design principles for monolithic optoelectronic integrated circuits (OEICs) through the implementation of an optical multi-token-ring network testbed system. Monolithic smart pixel CMOS OEICs are of paramount importance to high performance networks, communication switches, computer interfaces, and parallel signal processing for demanding future multimedia applications. The general testbed system is called Reconfigurable Translucent Smart Pixel Array (R-Transpar) and includes a field programmable gate array (FPGA), a transimpedance receiver array, and an optoelectronic very large-scale integrated (OE-VLSI) smart pixel array. The FPGA is an Altera FLEX10K 100E chip the performs logic functions and receives inputs from the transimpedance receiver array. A monolithic (OE-VLSI) smart pixel device containing an array of 4 * 4 vertical-cavity surface-emitting lasers (VCSELs) spatially interlaced with an array of 4 * 4 metal-semiconductor-metal (MSM) detectors connects to these devices and performs optical input-output functions. There components are mounted on a printed circuit board for testing and evaluation of integrated monolithic OEIC designs and various optical interconnection techniques. The system moves information between nodes by transferring 3-D optical packets in free space or through fiber image guides. The R-Transpar system is reconfigurable to test different network protocols and signal processing functions. In its operation as a 3-D multi-token-ring network, we use a specific version of the system called Transpar-Token-ring (Transpar-TR) that uses novel time-division multiplexed (TDM) network node addressing to enhance channel utilization and throughput. Host computers interface with the system via a high-speed digital I/O board that sends commands for networking and application algorithm operations. We describe the system operation and experimental results in detail.
机译:本研究探讨了通过实现光学多象环网测试平台系统的单片光电集成电路(OEIC)的架构和设计原理。单片智能像素CMOS OEIC对高性能网络,通信交换机,计算机接口以及用于要求未来多媒体应用的并行信号处理至关重要。一般测试的系统称为可重新配置的半透明智能像素阵列(R-incorment),并且包括现场可编程门阵列(FPGA),跨阻抗接收器阵列和光电非常大规模集成(OE-VLSI)智能像素阵列。 FPGA是Altera Flex10K 100E芯片执行逻辑功能并从跨阻抗接收器阵列接收输入。包含4×4垂直腔表面发射激光器(VCSEL)的阵列的单片(OE-VLSI)智能像素装置,其空间上与4 * 4金属 - 半导体 - 金属(MSM)检测器的阵列隔离连接到这些器件和执行光学输入输出功能。将部件安装在印刷电路板上,用于测试和评估集成的单片OEIC设计和各种光学互连技术。系统通过在自由空间中或通过光纤图像引导件中传送3-D光学分组来移动节点之间的信息。 R-Dronal系统可重新配置以测试不同的网络协议和信号处理功能。在其作为三维多象环网的操作中,我们使用称为透明令牌环(Tranking-Tr)的系统的特定版本,该系统使用新的时分复用(TDM)网络节点寻址来增强信道利用率和吞吐量。主机通过高速数字I / O板与系统接口,可发送用于网络和应用程序算法操作的命令。我们详细描述了系统操作和实验结果。

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