Efficient control structures for digital programmable retinas

摘要

A digital programmable artificial retina (PAR) is a functional extension of a CMOS imager, in which every pixel is fitted with a local ADC and a tiny digital programmable processor. From an architectural viewpoint, a PAR is an SIMD array processor with local optical input. A PAR is aimed at processing images on-site (where they are sensed) until they can be output from the array under concentrated form. The overall goal is to get compact, fast and inexpensive vision systems, in particular for robotics applications. A 256 * 256 PAR with up to a few tens bits of local memory per pixel (allowing image sequence processing) is now within reach at reasonable cost. However, whereas the local memory size benefits quadratically from the feature size decrease, wiring density improvement can only be linear, at best. So control should become more complex with the danger of a growing proportion of the digital pixel area being devoted to instruction or address decoding. We propose efficient scalable solutions to this problem at the architectural, circuit and topological levels, which attempt to minimise both silicon area and power consumption.