The introduction of underfill, a real breakthrough in the flip chip package industry, gave the solder interconnection technology an unforeseen mechanical robustness and a significant increase in flip-chip solder fatigue resistance. Derivatives from this technology (i.e.x plastic ball grid arrays-PBGA, ceramic ball grid array-CBGA, chip scale packages-CSP, etc.) have been developed in recent years. In essence, these new technologies are meant to mimic the product robustness and reliability performance of the original controlled collapse chip connection (C4) first used by IBM on solid logic technology (SLT) for flip chips in the early sixties. These new technologies were developed to increase both mechanical robustness and fatigue resistance. New interconnection geometry, using essentially the same solder materials as the original C4 joints, were introduced to overcome larger mismatches in components displacements during temperature excursions and to support larger loading such as heatsinks, etc. For electronic packaging, the use of these new interconnections has been as successful as the original C4 technology. However, the environments for these packages became increasingly demanding. Failure mechanisms, believed to be eliminated, or at least alleviated by the new package designs, are again threatening their untegrity and reliability. Dynamic loading, which is induced during vibration and mechanical shocks, results in reliability detractors for CSP and DCA packages in particular. Analytical models and simulation of these mechanisms are proposed. Reliability requirements for flip chip (FC), in particular large die and flip chip on board (FCOB) also referred as direct chip attach (DCA), mandate underfill or encapsulation processes. These processes are well characterized an commonly used on manufacturing lines across the industry to meet the performance and quality goals for electronic packages. New package geometries (smaller gaps, denser arrays, and longer flow distances) that are being developed pose new challenges to the underfilling process as practiced today. For example, new constraints on fluid flow paths will likely require materials with altered chemistries and smaller particle sizes. In addition, the flow out time with traditional materials in these new applications could cause productivity issues on production lines. This paper describes key parameters affecting the flow-out time with new fluid formulations on large test die with small PCB-to-chip gaps.
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