Optimum voltage swing on on-chip and off-chip interconnects

摘要

A reduced voltage swing is often used to save power on interconnects. We investigate what is the optimum voltage swing for minimum power in different situations. This is done by modelling power versus voltage swing of the driver-interconnect-receiver combination, and look for the minimum of this power consumption. The results are illustrated by examples from a 0.18 μm CMOS process.