Enhanced Parallel Processing in Wide Registers

摘要

Wide computer registers offer opportunities to exploit parallel processing. Instead of using hardware assists to partition a register into independent non-interacting fields, the multiple data elements can borrow and carry from elements to the left, and yet be accurately separated. Algorithms can be designed so that they execute within the allocated precision. Their floating point or irrational constants (e.g., cosines) are converted into integer numerators with floating point denominators. The denominators are then merged into scaling terms. To control the dynamic range and thus require less bits of precision per element, shift rights can be used. The effect of the average truncation errors is analyzed and a technique shown to minimize this average error.