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On the Tracking Performance of a Galileo/GPS Receiver Based on Hybrid FPGA/DSP Board

机译:基于混合FPGA / DSP板的伽利略/ GPS接收机的跟踪性能

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The design of receivers in the field of Global Navigation Satellite Systems (GNSS) is going through a fundamental stage of development. As a matter of fact, the market is showing the need of having user terminals with improved performance, and able to match the requirements of different services and applications related to positioning. On the other hand, the constant advancements on the way leading to the modernization of the actual Global Positioning System (GPS) and the development of the new European Satellite System, Galileo, are driving the design of new architectures for the future GNSS receivers able to manage signals with high sampling rates. Considering this framework, the solution of developing such user terminals on reconfigurable platforms has grown in importance. From the manufacturers point of view, such an approach will make possible to upgrade and reconfigure the system with new features, while from the research point of view it will make easier to perform tests on signal processing algorithms for the new modulation schemes foreseen by the future GNSS signal requirements. In this light, this paper introduces a work for the realization of a test receiver based on Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs), design according to the Software Defined Radio (SDR) philosophy. The test receiver assure a 100% level of flexibility for each one of its functional blocks. Starting from the justification for the hardware tools selected, the paper reports the last results about the analysis of the system performance going through the details of the architecture description, focusing the attention on the Code and Carrier Tracking Loops. Since the new Galileo modulated Signals-In-Space (SIS) are not yet available, a software version of an input signal generator has been realised, and its realization will be discussed taking care of the real-time constraints. Results of the Tracking Jitter Error (TJE) for various modulation schemes implemented on the described architecture are presented, comparing them with simulative results.
机译:全球导航卫星系统(GNSS)领域的接收器设计正在经历一个基本的发展阶段。事实上,市场表明需要具有改进性能的用户终端,并且能够匹配与定位相关的不同服务和应用的要求。另一方面,导致现代化的全球定位系统(GPS)和新欧洲卫星系统的发展的恒定进步正在推动能够为未来GNSS接收器的新架构设计管理具有高采样率的信号。考虑到这一框架,在可重新配置平台上开发此类用户终端的解决方案非常重要。从制造商的角度来看,这种方法将使能够以新功能升级和重新配置系统,而在研究的角度来看,它将更轻松地对未来预见的新调制方案的信号处理算法进行测试GNSS信号要求。在这种光中,本文介绍了一种基于现场可编程门阵列(FPGA)和数字信号处理器(DSP)的测试接收器的工作,根据软件定义的无线电(SDR)哲学设计。测试接收器确保其每个功能块的每个功能块100%的灵活性。从所选硬件工具的理由开始,纸张报告了关于通过架构描述的详细信息分析系统性能的最后结果,将注意力集中在代码和载波跟踪环上。由于新的伽利略调制信号空间(SIS)尚不可用,因此已经实现了一种输入信号发生器的软件版本,并且将讨论其实现,以处理实时约束。提出了在所描述的体系结构上实现的各种调制方案的跟踪抖动误差(TJE)的结果,将它们与模拟结果进行比较。

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