A low-power multi-modulus divider in 0.6 /spl mu/m digital CMOS technology

摘要

A 1.4 GHz programmable divider, whose modulus can be varied from 16 to 31, is presented with improved timing of the multi-modulus divider structure and high-speed low-voltage embedded logic D-flip flop. Programmability is achieved by gating the feedback signal of the first latch of the divide-by-2 blocks. For high-speed operation, the first control stage is implemented with a simple pseudo-NMOS logic gate. The programmable divider has been simulated in a 0.6 /spl mu/m digital CMOS technology with 13 mW power consumption at 2.7 V power supply and 1.4 GHz maximum frequency.