A SCALABLE COMPUTING AND MEMORY ARCHITECTURE FOR VARIABLE BLOCKSIZE MOTION ESTIMATION ON FIELD-PROGRAMMABLE GATE ARRAYS

摘要

In this paper, we investigate the use of Field-ProgrammableGate Arrays (FPGAs) in the design of a highly scalableVariable Block Size Motion Estimation architecture for theH.264/AVC video encoding standard. The scalability of thearchitecture allows one to incorporate the system into lowcost single FPGA solutions for low-resolution videoencoding applications as well as into high performancemulti-FPGA solutions targeting high-resolutionapplications. To overcome the performance gap betweenFPGAs and Application Specific Integrated Circuits, ouralgorithm intelligently increases its parallelism as thedesign scales while minimizing the use of memorybandwidth. The core computing unit of the architecture isimplemented on FPGAs and its performance is reported. Itis shown that the computing unit is able to achieve 28frames per second (fps) performance for 640x480resolution VGA video while incurring only 4% deviceutilization on a Xilinx XC5VLX330 FPGA. With 8computing units at 37% device utilization, the architectureis able to achieve 31 fps performance for encoding full1920x 1088 progressive HDTV video.