This document describes an innovative approach for simulating a DSP processor with VLIW architecture, the simulator structure and shows a performance comparison with a state of the arts simulation tool. The simulation approach is based on a three-dimensional (phase, time, operation) representation of the pipeline in order to "grab" in a certain time stamp the complete processor status, taking into account the current status and the following. This approach allows to accurately simulate the C6x behavior reducing the simulation time compared with the others on-market available simulators. Moreover the VLIW simulator generating dynamically the instruction set is a flexible tool for the hardware-software co-design.
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