For real-time image-processing applications, a highly parallel system that exploits parallelism is desirable. A content addressable memory (CAM) that performs parallel data processing with words as the basic unit is a promising component of acompact highly parallel image processing system because of its suitability for LSI implementation. Conventional CAM LSIs, however, do not have efficient transfer of data between words [1]. This limits image-processing applications. Moreover, they do nothave enough capacity. More chips are required for pixel-order parallelism. This 1Mb CAM LSI has dedicated functions for image processing, including data transfer. It performs two-dimensional pixel-parallel or cellular automation processing [2]. Since ithas 16k words or processing elements (PEs) which process 128×128 pixels, a board-sized fully pixel-parallel image-processing system can be implemented using several chips.
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