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A 52Mb/s universal DSL transceiver IC

机译:一个52MB / s通用DSL收发器IC

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摘要

A twisted-pair quadrature amplitude modulation (QAM) transceiver IC accommodates data rates from 0 to 52Mb/s. The QAM transceiver is a monolithic mixed signal device implemented in 0.35μm four-level metal single-poly CMOS. The transceiversupports 4-, 16-, 32-, 64-, 128-, and 256-QAM modulation formats and operates at symbols rates as high as 13MBaud. The transceiver chip contains a fully-integrated transmitter, including ATM UTOPIA or synchronous input interface, packet-formatting logic,Reed-Solomon forward error correction (FEC) encoding, a rate-adaptive QAM modulator and a lob D/A converter [11. The receiver portion of the transceiver chip consists of a high-precision 10b A/D converter, a programmable rate QAM demodulator, all-digitalclock and carrier recovery loops, powerful adaptive filters to provide rejection of narrowband interferers and the equalization of severe channel distortions, FEC decoding, ATM UTOPIA or synchronous output interface and an analog phase-lock loop forinternal clock generation from a single crystal reference [2, 3]. The QAM transceiver may be used in applications such as asymmetric digital subscriber line (ADSL) and very high-speed digital subscriber line (VDSL) services.
机译:从0到52MB双绞线正交幅度调制(QAM)收发器IC容纳的数据速率/秒。所述QAM收发器处于0.35微米四能级金属单层多晶硅CMOS实现的单片混合信号装置。的transceiversupports 4-,16-,32-,64-,128-,和256-QAM调制格式和符号在率高达13MBaud操作。该收发器芯片包含一个完全集成的发射器,包括ATM UTOPIA或同步输入接口,分组格式化逻辑电路,里德 - 所罗门前向纠错(FEC)编码,速率自适应QAM调制器和LOB d / A转换器[11。收发机芯片的接收器部分包括一个高精度10B A / d转换器,一个可编程速率QAM解调器,全digitalclock和载波恢复环路,强大的自适应滤波器,以提供抑制窄带干扰信号的和严重的信道失真的均衡, FEC解码,ATM UTOPIA或同步输出接口和从单晶参考文献[2,3]的模拟锁相环forinternal时钟产生。收发机可以在应用中使用,如非对称数字用户线路(ADSL)和超高速数字用户线(VDSL)服务QAM。

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