This paper describes the Design for Testability and test synthesis of a modular video-processing chip named Co-Processor Array (CPA). A core-based test method has been implemented to enable efficient test pattern generation and verification. Themain challenges of this work are the test clock strategy, test control, Design for Testability for the various blocks and busses, and test protocol expansion and simulation at chip-level. The core-based test strategy proved to be well suited forintegrated circuits with a modular structure like the CPA. Reduction of time-to-market for redesigns and new versions is achieved with this method by reusing cores including Design for Testability and test pattern generation.
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