Next-generation microprocessors and DSPs challenge power systems designers by lowering supply voltages while increasing the system's power consumption. It becomes a difficult task to keep the supply voltages within requirements, especially at high slew-rate transitions from sleeping mode to full power operation and backwards. Simple "rule-of-thumb" estimations lead to excessive decoupling or last-moment changes of the design. Computer simulation is a useful tool to confirm the design, but the optimum selection of power supply parameters is still a problem. A cost-effective and reliable solution requires an accurate and practical analysis of the power supply system during high slew-rate transients. The load current transient analysis of synchronous buck converter with theoretically fastest hysteretic controller is presented in this paper. The analyzed model includes both converter and controller characteristics along with the output capacitor and power bus parasitics. Analytical equations are derived for voltage and current waveforms during the load current step-up and step-down transients. The impact of different parameters, including parasitics, is studied by using Mathcad software. The test measurements at different conditions are in good agreement with the analytically derived waveforms. This paper provides a fulfilled analysis and gives recommendations on how to optimize power distribution systems.
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