Target processor and co-verification environment independent adapter - a technology to shorten cycle-time for retargeting TI processor simulators in HW/SW co-verification environments

摘要

Hardware-Software Co-Verification is essential for design and verification of embedded Systems at the early development stages to reduce development cycle time. A number of Co-Verification environments are available from EDA vendors to simulatesuch designs, each with its own interfaces and mechanisms. TI provides Co-Verification models for its DSP devices and cDSP megamodules in these environments. We present an approach that enables TI's Instruction Set Simulators to seamlessly be integratedin these environments. This hides the EDA environment specific interfaces from the simulator/ model developer thereby shortening the Co-Verification model development cycle times.