Impact of Laterally Asymmetric Channel and Gate Stack Design on Device Performance of Surrounding Gate MOSFETs: A Modeling and Simulation Study

摘要

A new device architecture, laterally asymmetric channel gate stack (LACGAS) SGT has been proposed and a two-dimensional analytical model is presented to study the impact of this structure on the device characteristics. A parabolic potential profile is assumed to solve the Poisson equation in cylindrical coordinates and the expressions for surface potential, electric field and threshold voltage have been deduced. The analysis is extended to predict the current-voltage characteristics. It is demonstrated that LACGAS leads to suppression of short channel effects such as threshold voltage (V_(th)) roll-off, drain induced barrier lowering (DIBL) and hot carrier effects. It also improves the transport efficiency owing to a greater gate control which is achieved by incorporating the stack architecture. Furthermore, LACGAS design also enables to obtain a high current drivability and enhancement in transconductance. The effectiveness of LACGAS design has been examined by studying the device characteristics over a wide range of parameters and it is shown that LACGAS offers superior characteristics as compared to conventional and laterally asymmetric channel (LAC) devices. The results so obtained have been compared with simulated data obtained from the device simulator ATLAS 3D and are found to be in good agreement.