In this paper, we present a method to take executions schemes into account during High-Level synthesis. We aim at evenly distributing the workload of functional units statically, i.e at compile-time. Activating a functional unit more often than any other can be disastrous for the reliability of the circuit (thermal shock). This method is intended for Control-flow intensive applications that generally exhibit complex behaviors. For this purpose, we first rely on a powerful internal graph representation to determine the activity of sets of nodes: we get measures on the performance of different assignments. Then a design space exploration is performed via a genetic algorithm that makes it possible to choose a correct assignment in term of load balance.
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