A Simple Polishing Technique for Removing the Entire Metallization Stack for Sub 100nm Device Technologies

摘要

The physical analysis of sub-100nm device technologies in many cases requires the total or partial removal of the multiple layers of metallization that route electrical signals and power through the device. There are two purposes for removing the metallization layers. The first is to inspect individual layers in a known failing circuit for damage or defects as the layers are sequentially removed. The second is to remove the entire metallization stack to gain access to the transistors for electrical characterization and/or additional physical analysis. This requires the transistor layer to remain intact and relatively planar from the top of contact down to substrate.