Computing Multidimensional DFTs Using Xilinx FPGAs

摘要

This paper reports on a reconfigurable computing architecture that takes advantage of the reduced computational requirements of the polynomial transform method for computing 2-D DFTs. An FPGA architecture is described that is capable of processing 24 512 × 512-pixel images per second. The proposed system is 46% more area efficient than a row-column DFT processor implemented using the same technology.