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VHDL-based development of a 32-bit pipelined RISC processor for educational purposes

机译:基于VHDL的32位流水线RISC处理器的开发,用于教育目的

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This paper describes the ongoing activities in design education at the University of Stuttgart. It is decomposed into two steps. The first step is a course of one semester. There the students obtain basic design and architecture knowledge under the close guidance of an experienced advisor. For the second step, we have launched a little project, that comes as close as possible to real life experience: the design of the DLX, a 32-bit RISC processor. The project has been split into smaller tasks being handled autonomously by the students in a six months period. As a side effect a complete processor model is developed.
机译:本文介绍了斯图加特大学设计教育的持续活动。它被分解成两个步骤。第一步是一个学期的课程。在经验丰富的顾问的密切指导下,学生可以获得基本的设计和建筑知识。对于第二步,我们已经推出了一点项目,尽可能接近现实生活经验:DLX的设计,32位RISC处理器。该项目已被分为较小的任务,在六个月内学生自主处理。作为副作用,开发了完整的处理器模型。

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