A complete suite of algorithms for parallelizing compilers to generate efficient SPMD code for SOR problems is presented. By applying unimodular transformation before loop tiling and parallelization, the number of messages per iteration per processor is reduced from 3/sup n/-1 in the conventional parallel SOR algorithm to 2/sup n/-1, where n is the dimensionality of the data set. To maintain the memory-scalability, a novel approach to use the local dynamic memory of parallel processors to implement the skewed data set is proposed.
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机译：提出了一个完整的套件，用于并行化编译器以生成用于SOR问题的有效SPMD代码。通过在循环平铺和并行化之前应用单模转换，每个处理器的每次迭代的消息数量从传统的并行SOR算法中的3 / sup n / -1减少到2 / sup n / -1，其中n是维度的维度数据集。为了保持内存可伸缩性，提出了一种使用并行处理器的局部动态存储器来实现偏移数据集的新方法。
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