This paper reports a methodology that is able to reduce the `time to money for the IC Industry' by increasing the yield and reliability of devices fabricated in an immature process. This is achieved through both automated generation of redundant vias and methods of efficiently estimating the impact of such modification on the device yield. The approach consists of identifying non-redundant vias that are contained within a VLSI design together with a method of generating associated redundant vias. The number of redundant/non-redundant vias before and after the modification procedure is efficiently estimated using a sampling technique. Hence, only a fraction of the device need be modified and analyzed. This enables efficient comparison of different modification strategies, taking into account not only yield mechanisms that are improved but also those that may be adversely affected by the introduction of new vias and any associated conductor material.
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