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An efficient and high-performances CMOS op amp with rail-to-rail mode and high CMRR

机译:具有轨到铁路模式和高级CMOS运算放大器的高效且高性能的CMOS运算放大器和高CMRR

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In this paper, we present a new structure of a CMOS Op Amp offering high performances differential frequency response with high CMRR, high slew rate and input/output rail-to-rail mode. These performances are due both to a new efficient gain stage with a compact layout and to a simple way to obtain a high CMRR. Simulation experiments have been performed with three different (0.8 /spl mu/m, 1.2 /spl mu/m, 2.4 /spl mu/m) CMOS technologies. In particular for the 0.8 /spl mu/m one, the main performances-under single 5 V power supply are a unity gain bandwidth of 40 MHz, a phase margin of 63 degrees, a slew rate of 60 V//spl mu/s, all performed on heavy load such as 2.5 k/spl Omega//spl par/20 pF. Simulated results have been experimentally confirmed for the 2.4 /spl mu/m CMOS technology for which we have measured a low frequency CMRR of 100 dB.
机译:在本文中,我们提出了一种新的CMOS运算放大器的新结构,提供高性能差分频率响应,高CMRR,高压速率和输入/输出轨到轨模式。这些性能既由于新的高效增益阶段而具有紧凑的布局,并以获得高CMRR的简单方法。用三种不同(0.8 / SPL MU / M,1.2 / SPL MU / M,2.4 / SPL MU / M)CMOS技术进行了模拟实验。特别是对于0.8 / SPL MU / M ONE,主要性能 - 在单个5 V电源下是40 MHz的单位增益带宽,相位裕度为63度,转换速率为60 V // SCL MU / S。 ,都在重载中执行,例如2.5 k / spl omega // spl / 20 pf。对于2.4 / SPL MU / M CMOS技术,已经通过实验证实了模拟结果,我们测量了100 dB的低频CMRR。

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