Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop

摘要

In this paper we propose a novel energy efficient radiation hardened dual modular true single-phase clock flip-flop (DM-TSPC FF). We show that the existing radiation hardened TSPC flip-flop designs, viz. TSPC-DICE and TSPCQuatro, have SEU tolerant latching circuits but can get upset when radiation strikes occur in the sampling circuits. Our proposed DM-TSPC FF elegantly circumvents this problem without increasing area. We have implemented all the designs in UMC 28nm technology node. We report that our proposed DM-TSPC FF has 76.16% less power-delay product (PDP) as compared to TSPC-DICE and 80.76% less PDP as compared to TSPC-Quatro. DM-TSPC FF consumes extremely low energy. It consumes 0.71 fJ compared to TSPC-DICE which consumes 6.62 fJ and TSPC-Quatro which consumes 8.43 fJ. Apart from this, we have compared the DM-TSPC flip-flop designs with other TSPC flip-flops by implementing ISCAS'89 benchmark circuits using these flip-flops. Even for large sequential designs, we find that DM-TSPC based designs consume only about 50% of the power compared to TSPC-DICE based designs and only about 20% power compared to TSPC-Quatro based designs.