A read channel two-chip processor for rewritable 3.5" magneto-optical disk drives is presented. The front-end includes an automatic gain control (AGC) circuit, a programmable 6-pole 2-zero equiripple filter/equalizer, a DC restore circuit, and pulse detectors. The back-end contains a frequency synthesizer and a data synchronizer with 3:1 operating range to support a constant density recording with 8-24 Mbit/s data rate in 2,7 RLL format. The architecture of the chip provides a high degree of programmability through a serial microprocessor interface, fast switching (1 /spl mu/s) between sector mark and data modes, and four levels of power management in a 1.5 /spl mu/m 4 GHz BiCMOS process. With a nominal power supply of 5 V, the chip set dissipates 600 mW during normal operation and 1 mW during sleep mode.
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机译：提出了一种用于可重写3.5“磁光磁盘驱动器的读取通道两芯片处理器。前端包括自动增益控制（AGC）电路，可编程6极2-ox Equiripple滤波器/均衡器，DC恢复电路和脉冲检测器。后端包含频率合成器和带3：1的数据同步器，以支持2,7 RLL格式的8-24 Mbit / s数据速率的恒定密度记录。芯片的架构通过串行微处理器接口，扇形标记和数据模式之间的快速切换（> 1 / SPL MU / S）提供高度可编程性，以及1.5 / SPL MU / M 4 GHz BICMOS过程中的四个电源管理。使用标称电源为5 V，芯片组在正常操作期间耗散600 mW，睡眠模式下为1兆瓦。
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