A C-testable design, which requires only five test patterns, for dynamic clocked differential cascode voltage switch (DCVS) GF(2/sup m/) multiplier circuit is proposed. The hardware overhead includes two extra control lines and m XOR gates. For simplicity, the area overhead in transistor counts is /sup 1//sub 3m+1/ for a GF(2/sup m/) multiplier.
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机译：提出了一种用于仅需要五个测试模式的C可测试的设计，用于动态时钟差分共级电压开关（DCVS）GF（2 / SUP M /）乘法器电路。硬件开销包括两个额外的控制线和M XOR门。为简单起见，晶体管计数中的区域开销是/ SUP 1 // SUB 3M + 1 /用于GF（2 / SUP M /）乘数。
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