Alpha architecture and first implementation

摘要

Summary form only given. Alpha is a new 64-b RISC (reduced instruction set computer) architecture designed to facilitate superpipelined and superscalar implementations. EV4, the first implementation of the Alpha architecture, is a 200-MHz custom VLSI CPU with a peak issue rate of 400 MIPs. EV4 is implemented in Digital's 0.75- mu m 3.3-V CMOS technology, contains 1.68 M transistors on a 16.8-mm*13.9-mm chip, and is packaged in a 431-pin PGA. The Alpha architecture, besides supporting a variety of integer and floating point data types, emphasizes pipelining, memory synchronization, and memory access. To facilitate application of the chip on a broad spectrum of applications, EV4 connects directly to an external writeback backup cache built from industry-standard static RAMs.