The author introduces a new way to organize memory elements into scan chains for built-in self-testable data path logic. The goal of the procedure is to minimize the hardware overhead and performance impact associated with pseudo-random built-in self-test (PR-BIST) techniques by organizing the memory elements such that some of the logic required for BIST and scan operations is also used during normal operation. The author identifies function types that are well suited for implementation with the register designs required for BIST and shows that these function types are found in data path designs. Functional use is made of the BIST logic by organizing the memory elements in the design into orthogonal scan chains. A data path design example is used to compare an implementation using a normal BIST configuration to one using the orthogonal configuration.
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