A novel cell switching architecture for asynchronous transfer mode (ATM)-based networks is presented. The proposed helical switch is a multistage interconnection network which implements the self-routing technique with efficient buffer sharing. Although the switch may route cells along multiple paths, the connection-oriented mode required by the ATM-based network is supported. Cell sequence integrity is guaranteed by introducing a virtual helix which forces cells routed along different paths to proceed in order and fill the internal buffers uniformly. Under a uniform traffic pattern, it is shown that the minimum achievable throughput is 5/6 per output line.
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