首页> 外文会议>International Conference on Computer Design >Performance optimization by wire and buffer sizing under the transmission line model
【24h】

Performance optimization by wire and buffer sizing under the transmission line model

机译:传输线模型下电线和缓冲尺寸的性能优化

获取原文

摘要

As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the transmission line behavior for delay computation. We present in this paper an analytical formula for the delay computation under the transmission line model. Extensive simulations with SPICE show the high fidelity of the formula. Compared with previous works [8, 11], our model leads to smaller average errors in delay estimation. Based on this formula, we show the property that the minimum delay for a transmission line with reflection occurs when the number of round trips is minimized (i.e., equals one). Besides, we show that the delay of a circuit path is a posynomial junction in wire and buffer sizes, implying that a local optimum is equal to the global optimum. Thus, we can apply any efficient search algorithm such as the well-known gradient search procedure to compute the globally optimal solution. Experimental results show that simultaneous wire and buffer sizing is very effective for performance optimization under the transmission line model.
机译:随着工作频率的增加,信号赫兹和信号的上升时间小于或与线的飞行时间延迟相当,需要考虑用于延迟计算的传输线行为。我们在本文中呈现了传输线模型下的延迟计算的分析公式。随着香料的广泛模拟显示了公式的高保真度。与以前的作品相比[8,11],我们的模型导致延迟估计的较小平均误差。基于该公式,我们示出了当圆形跳闸的数量最小化时发生具有反射的传输线的最小延迟的特性(即,等于一个)。此外,我们表明电路路径的延迟是电线和缓冲尺寸的姿态结,这意味着局部最佳值等于全球最佳。因此,我们可以应用任何有效的搜索算法,例如众所周知的梯度搜索过程来计算全局最佳解决方案。实验结果表明,同时电线和缓冲尺寸对于传输线模型下的性能优化非常有效。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号