Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice of moves is fairly straightforward. In this work, we study the fired-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SOCs. We empirically show that the fired-outline floorplan problem instances are significantly harder than the well-researched instances without fired outline. Furthermore, we suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline-free and fired-outline modes. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported ([16]). A similar slack computation is possible with many other floorplan representations. In all cases, the slowdown is by a constant factor - roughly 2x.
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