Sleipnir. An instruction-level simulator generator

摘要

Instruction-level simulators occupy a central role in the software development for embedded processors. They provide a convenient virtual platform for testing, debugging and optimizing code. They can be made available long before any hardware is available, and are not as awkward to work with as test/evaluation boards. However, many available instruction-level simulators are lacking in desired functionality. Moreover, instruction-level simulators suitable to the task are tedious to write from scratch. This paper presents the Sleipnir simulator generator, a convenient tool for writing instruction-level simulators. Sleipnir allows simulators for simple architectures to be generated with a minimum of overhead, yet allows sufficient micro-architectural detail to be expressed to generate cycle accurate simulators for most embedded processors. Sleipnir has been used to successfully generate fast instruction-level simulators for six different architectures, including a RISC processor, two microcontrollers and three DSPs.