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Architectural synthesis of timed asynchronous systems

机译:定时异步系统的架构合成

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This paper describes a new method for architectural synthesis of timed asynchronous systems. Due to the variable delays associated with asynchronous resources, implicit schedules are created by the addition of supplementary constraints betweenresources. Since the number of schedules grows exponentially with respect to the size of the given data flow graph, pruning techniques are introduced which dramatically improve runtime without significantly affecting the quality of the results. Using acombination of data and resource constraints, as well as an analysis of bounded delay information, our method determines the minimum number of resources and registers needed to implement a given schedule. Results are demonstrated using some high-levelsynthesis benchmark circuits and an industrial example.
机译:本文介绍了一种用于架构架构合成定时异步系统的方法。由于与异步资源相关的可变延迟,通过添加补充资金之间的补充约束来创建隐式调度。由于时间表的数量呈指数相对于给定数据流程图的大小,因此引入了剪枝技术,其显着改善了运行时,而不会显着影响结果的质量。使用数据和资源约束的酰胺,以及对有界延迟信息的分析,我们的方法确定实现给定计划所需的最小资源数量和寄存器。使用一些高级别合成的基准电路和工业例子来证明结果。

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