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Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects

机译:芯片电容和电感串扰噪声的定量预测与电感串扰线横截面区域的探讨

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摘要

Capacitive and inductive crosstalk noises are expected to be more serious in advanced technologies. However, capacitive and inductive crosstalk noises in the future have not been concurrently and sufficiently discussed quantitatively, though capacitive crosstalk noise has been intensively studied solely as a primary factor of interconnect delay variation. This paper quantitatively predicts the impact of capacitive and inductive crosstalk in prospective processes, and reveals that interconnect scaling strategies strongly affect relative dominance between capacitive and inductive coupling. Our prediction also makes the point that the interconnect resistance significantly influences both inductive coupling noise and propagation delay. We then evaluate a tradeoff between wire cross-sectional area and worst-case propagation delay focusing on inductive coupling noise, and show that an appropriate selection of wire cross-section can reduce delay uncertainty by the small sacrifice of propagation delay.
机译:电容和电感串扰噪声预计在先进技术方面会更加严重。然而,未来的电容和电感串扰噪声尚未定量且充分地讨论,但是电容性串扰噪声被广泛地研究了互连延迟变化的主要因素。本文定量地预测了电容性和电感串扰在预期过程中的影响,并揭示了互连缩放策略强烈影响电容和电感耦合之间的相对优势。我们的预测还使得互连电阻显着地影响抵抗耦合噪声和传播延迟的程度。然后,我们评估导线的横截面面积和最坏情况下的传播延迟着眼于电感耦合噪声,并表明,导线截面的适当选择可以通过传播延迟的小的牺牲减少延迟的不确定性之间的折衷。

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