A Practical Assurance Approach for Multi-Cores (MCs) Within Safety-Critical Software Applications

摘要

Single-core processors are increasingly difficult to source with microprocessor manufacturers moving into a Multi-Core (MC) arms race for energy efficiency and performance improvement. However, performance gains by MC utilisation of many cores and shared resources brings challenges for qualification; e.g. interference paths that impact Worst-Case Execution Time (WCET). For high-integrity aviation systems (e.g. DO-178B/C level A and B) these challenges need to be re-solved for confidence to be gained to accept these MC based systems. MC is the future and we need a way to qualify and accept MC based safety-critical systems into service. This paper illustrates a practical implementation strategy for MCs on a safety-critical system within a UK airborne system that is currently undergoing an external qualification assessment. This paper documents the strategy in terms of recommendations based upon the development, verification, and validation activities undertaken. The strategy has been refined based upon our experiences'. The approach is based upon a diverse strategy which adopts quantitative and qualitative evidence.