Stately: An FSM Design Tool.

摘要

Finite state machines (FSMs) are at the heart of many digital circuits, in particular microprocessors such as the IoT-oriented Cephalopode processor we are implementing as part of the Octopi project.We frequently encounter two practical difficulties with FSM design: first, in the case of Mealy machines state transitions and output logic can have complex and overlapping conditions, which are difficult to maintain and comprehend if separated; and second, there is a tension between clarity and clock cycles with respect to the insertion of intermediate states.To address these in the context of the Cephalopode processor we developed the open-source tool Stately, a visual environment for designing finite state machines. States are organized spatially, individually programmed in a simple domain-specific language, and the resulting machine can be compiled to HFL code for the VossII hardware design and simulation platform.In addition to allowing the intermingling of transitions and output declarations, Stately introduces a mechanism by which chosen states can be merged during compilation. While only a modest semantic extension, it resolves several clarity-efficiency tradeoffs while retaining a clear visual interpretation. Other features include lightweight simulation for rudimentary testing, and extensive error-checking.