This paper is focused on the research of instruction scheduling technology for clustered VLIW architecture. A novel scheduling technology is presented in this work, which exploits the tradeoff between the balancing of distribution of instructions amongst clusters and reduction of the amount of inter-cluster data communications, and guides the cluster assign and cycle schedule of instructions by estimating the influence of these two factors on execution cycles. Results show that large improvement can be achieved in performance. The speed-ups achieved for bus connected architectures compared with list scheduling are up to 60.9%, while average speed-ups rage from 45.4% (2-Clusters) to up to 56.0% (4-Clusters). While the speed-ups achieved for register file connected architectures compared with list scheduling are up to 46.0%, while average speed-ups rage from 29.2% (2-Clusters) to up to 41.3% (4-Clusters).
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