A Low-Power Third-Order Passive Continuous-Time Sigma-Delta Modulator Using FinFET

摘要

FinFETs are known to be one of the promising devices for sub-50 nm regime. It involves better channel control, reduced short channel effects and low leakage current. A third-order continuous-time sigma-delta modulator presented in this paper is constructed by adding a capacitor to the stable second-order low-pass RC filter. It improves the quantization noise shaping and linearity of the modulator without increasing the power dissipation. A low-power, low-offset SR latch-based clocked comparator is used as quantizer. The designed modulator is implemented in FinFET 16 nm process, achieves the result of SNDR of 64 dB, ENOB of 10.5 bits, power dissipation of 48 μW and operating with 1 V supply voltage. It is suitable for low-power ADC in biomedical applications with a signal bandwidth of 4 kHz.